N=0, GRP=0, ALIGN=0, P=0, RV=0, EN=0, FB=0, NFCS=00, NFEN=0, GODF=0, INV=0
Output Phase Switching Control Register
| UF | Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. |
| VF | Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. |
| WF | Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. |
| Reserved | This bit is read as 0. The write value should be 0. |
| U | Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) |
| V | Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) |
| W | Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) |
| Reserved | This bit is read as 0. The write value should be 0. |
| EN | Enable-Phase Output Control 0 (0): Not Output(Hi-Z external terminals). 1 (1): Output |
| Reserved | These bits are read as 0000000. The write value should be 0000000. |
| FB | External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. 0 (0): Select the external input. 1 (1): Select the soft setting(OPSCR.UF, VF, WF). |
| P | Positive-Phase Output (P) Control 0 (0): Level signal output 1 (1): PWM signal output (PWM of GPT0) |
| N | Negative-Phase Output (N) Control 0 (0): Level signal output 1 (1): PWM signal output (PWM of GPT0) |
| INV | Invert-Phase Output Control 0 (0): Positive Logic (Active High)output 1 (1): Negative Logic (Active Low)output |
| RV | Output phase rotation direction reversal 0 (0): U/V/W-Phase output 1 (1): Output to reverse the V / W-phase |
| ALIGN | Input phase alignment 0 (0): Input phase is aligned to PCLK. 1 (1): Input phase is aligned PWM. |
| Reserved | These bits are read as 00. The write value should be 00. |
| GRP | Output disabled source selection 0 (0): Select Group A output disable source 1 (1): Select Group B output disable source. |
| Reserved | This bit is read as 0. The write value should be 0. |
| GODF | Group output disable function 0 (0): This bit function is ignored. 1 (1): Group disable will clear OPSCR.EN Bit. |
| Reserved | This bit is read as 0. The write value should be 0. |
| Reserved | This bit is read as 0. The write value should be 0. |
| NFEN | External Input Noise Filter Enable 0 (0): Do not use a noise filter to the external input. 1 (1): Use a noise filter to the external input. |
| NFCS | External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. 0 (00): PCLK/1 1 (01): PCLK/4 2 (10): PCLK/16 3 (11): PCLK/64 |